Spin Read-out in Atomic Qubits in an All-Epitaxial Three-Dimensional Transistor
Result of the Month
FIG. 1. A vertically gated single electron transistor (SET) for high fidelity single-shot spin read-out fabricated using hydrogen resist lithography.
(a) A schematic of a vertically gated SET showing source, island, donor qubit, drain, and in-plane gate in the lower (1st) layer tuned by an additional top gate in the upper (2nd) layer aligned with ≤5nm accuracy. The two lithographic planes are vertically separated by 120nm of epitaxially grown silicon.
(b) Topographic STM image (50×50nm2, constant current mode) of the lower layer after dosing with PH3 with the phosphorus donor dot qubit patterned 19nm away from the SET island. The dimension of the SET island is 11×21nm2 which evaluates to 450 P atoms.
(c) Schematic illustration of a trench marker design (black lines) used for interlayer alignment that accommodates a STM patterned device. The dark blue leads in the lower half of the figure represent the microeter scale phosphorus doped STM-patterned contact leads to the single electron transistor formed in the first layer radiating out along the bottom of the trench from a central oval shaped plateau. Two cyan coloured leads represent the contacts to the top gate in the second layer radiating outward in a V-shape along separate trenches. The large rectangular phosphorus doped areas at the end of the trenches are subsequently aligned to surface metal used to form electrical contact to the buried device.
(d) STM image of the inner part of the marker. Silicon mass transport during the high temperature (1100oC) anneal as part of the initial surface preparation alters the original marker and results in features that can be exploited for alignment; if we follow a trench centreline towards the middle of the marker (white arrow), the surface first gently steps down a few nanometers at the trench exit (symbolized by the staircases), followed by a gradual raise towards a slightly protruded central plateau ~8nm in height (dotted white line).
The use of kinetic growth manipulation to optimize the regrowth surface for second layer lithography. Comparison of scanning tunnelling microscope images of the surface after the growth of a silicon encapsulation layer grown at a rate of ~0.2nm/min with (a-c) constant sample temperature of 250oC and (d-f) using kinetic growth manipulation with a rapid terminal anneal sequence up to 450oC in the final phases of the growth. Showcase of lithography on the surface of the encapsulation layer where (c) a square and (f) a single electron transistor structure are patterned. To illustrate the difficulty in validating lithography on a rough surface compared to a smooth surface only the upper half of the pattern outlines are marked with a dashed blue line.
The realization of the surface code for topological error correction is an essential step towards a universal quantum computer. For single-atom qubits in silicon, the need to control and read out qubits synchronously and in parallel requires the formation of a two-dimensional array of qubits with control electrodes patterned above and below this qubit layer. This vertical three-dimensional device architecture requires the ability to pattern dopants in multiple, vertically separated planes of the silicon crystal with nanometre precision interlayer alignment. Additionally, the dopants must not diffuse or segregate during the silicon encapsulation. Critical components of this architecture — such as nanowires, single-atom transistors and single-electron transistors – have been realized on one atomic plane by patterning phosphorus dopants in silicon using scanning tunneling microscope (STM) hydrogen resist lithography. In our latest work at the Centre for Quantum Computation & Communication Technology (University of New South Wales, Sydney), we extend this STM fabrication technique to three dimensions and demonstrate single-shot spin read-out with 97.9% measurement fidelity of a phosphorus dopant qubit within a vertically gated single-electron transistor with ≤ 5nm interlayer alignment accuracy. Our strategy ensures the formation of a fully crystalline transistor using just two atomic species: phosphorus and silicon.
To align two lithographic layers containing device components with respect to each other we pattern our devices on the bottom of wet etched trenches radiating outward from the flat bottom of a central depression. These trenches are etched ~350nm deep using a tetramethylammonium hydroxide etch before terminating with atomic hydrogen as an atomic scale mask for STM hydrogen resist lithography. The device is positioned at the intersection of the leads in the central region with its micrometer scale contact leads extending along the flat bottomed trenches (Fig. 1c-d). By using the centreline of the etched trenches as reference points we can align device structures from one layer to the other. In this way, lithography on the heavily stepped sides of the marker is avoided. In this way we can achieve a ≤5nm interlayer alignment accuracy.
To date precision donor devices have been encapsulated with epitaxial silicon grown at a comparatively low sample temperature of ~250oC needed to minimize P segregation (Fig. 2a). At such low temperatures mass transport of the Si atoms up and down the step edges is minimal and hence the shape of our alignment markers are only slightly modified during overgrowth. Although the growth is epitaxial, the resulting surface roughness (~1nm) makes lithography on the second plane challenging. This arises from the comparable height of a single dangling bond (0.17nm) and a Si adatom (0.14nm), where it is difficult to reliably distinguish between the two and validate high quality lithography as showcased in Fig. 2b-c. Whilst growing at higher substrate temperatures reduces surface roughness it can lead to the segregation of P atoms, especially for temperatures T>400oC, with P desorption occurring at 650oC. Possible diffusion and segregation of P atoms out of their precision placement therefore limits the thermal budget available for flattening the growth surface. To tackle this problem we exploit an adaptation of kinetic growth manipulation to smoothen the upper surface for a second cycle of STM lithography. The sample is kept at 250oC during most of the encapsulation, but we introduce a rapid thermal anneal sequence (6×1min, 450oC) in the last phase of the growth (Fig. 2d). In conventional kinetic growth manipulation anneals are applied to each monolayer of growth to improve surface flatness. Here we adapt this concept to increase the mobility of Si adatoms changing the growth mode from 2D islanding to step-flow growth allowing them to fill up existing vacancies in the lower layers without the diffusion of P. We find the surface roughness (RMS) after growing the encapsulation layer in this way reduces from 0.52±0.15nm to 0.15±0.03nm (Fig. 2b-e). The island size increases from a few atoms to ~100nm2. The flatter surface makes it possible to distinguish single dangling bonds and validate the quality of STM lithograph, as shown in Fig. 2f.
Authors: Matthias Koch, Joris G. Keizer, P. Prasanna, D. Keith, Matthew G. House, Eldad Peretz, and Michelle Y. Simmons
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